by Aenerine | May 3, 2020 | Blog Posts
It is approximately 3 years since I have tried to install the VmWare ESXI 6.0 and 6.5 on my small home server consisting of Zotac CI323 nano. The problem I was facing at that time was that the installation was unable to start and was stuck at “Kernel Loading...
by Aenerine | Mar 24, 2020 | Quick Posts
Whoever is familiar with Vivado already knows that it generates a huge quantity of files and that understanding a proper version control thus seems to be not as simple. The truth is, that Vivado’s design indeed consist of a plenty of different file types, but...
by Aenerine | Feb 29, 2020 | Quick Posts
I have noticed, that there are plenty of people, who do not know how to access the physical memory from linux (or for myself at least from Xilinx’s petalinux). Basically, a bare-metal application running on a CPU has direct access to memory by default, but...
by Aenerine | Feb 20, 2020 | FPGA
Most of newer ADCs and DACs tend to use the JESD204b/c standards simply due to higher performance requirements – the ever growing need for more usable Bandwidth, faster ADCs and DACs with increased resolution per sample and multi-channel implementations. The...
by Aenerine | Dec 28, 2019 | FPGA
Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks,...
