Vivado VersionControl

Vivado VersionControl

Whoever is familiar with Vivado already knows that it generates a huge quantity of files and that understanding a proper version control thus seems to be not as simple. The truth is, that Vivado’s design indeed consist of a plenty of different file types, but...
Accessing physical memory from user space

Accessing physical memory from user space

I have noticed, that there are plenty of people, who do not know how to access the physical memory from Linux (or for myself at least from Xilinx’s petalinux). Basically, a bare-metal application running on a CPU has direct access to memory by default, but...
FPGA LVDS Interfacing

FPGA LVDS Interfacing

Most of newer ADCs and DACs tend to use the JESD204b/c standards simply due to higher performance requirements – the ever growing need for more usable Bandwidth, faster ADCs and DACs with increased resolution per sample and multi-channel implementations. The...
IP Simulation with custom data

IP Simulation with custom data

Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks,...