by Aenerine | Aug 23, 2020 | FPGA
I remember that when I first searched for a guide on how to write linux kernel drivers, the first suggestion mentioned was that I should actually avoid writing kernel drivers. I would personally not suggest the same, though the fact remains that writing kernel drivers...
by Aenerine | Feb 20, 2020 | FPGA
Most of newer ADCs and DACs tend to use the JESD204b/c standards simply due to higher performance requirements – the ever growing need for more usable Bandwidth, faster ADCs and DACs with increased resolution per sample and multi-channel implementations. The...
by Aenerine | Dec 28, 2019 | FPGA
Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks,...
by Aenerine | Dec 23, 2019 | FPGA
by Aenerine | Nov 10, 2019 | FPGA
This topic will introduce some of the basic concept of using fixed point representation in FPGA. Because naturally in FPGAs, there is nothing like a “data format”,but only vector with some bits of data,its always a good idea to negotiate and or describe...
