IP Simulation with custom data

IP Simulation with custom data

Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks,...
Fixed Point & 2’S Complement

Fixed Point & 2’S Complement

This topic will introduce some of the basic concept of using fixed point representation in FPGA. Because naturally in FPGAs, there is nothing like a “data format”,but only vector with some bits of data,its always a good idea to negotiate and or describe...