Simple AXI4 Lite DUT Configuration for TB

Simple AXI4 Lite DUT Configuration for TB

Many of complex IPs and components nowadays use AXI4-Lite interface for configuration. Its a simple and sufficient protocol, but one may wonder how to easily configure such components with these types of interfaces from a Test – Bench. One of the options is to...
JTAG to AXI4

JTAG to AXI4

There are many possibilities of how you might debug your FPGA design. The most straigtforward way is to use the Chipscope (ILA – Integrated Logic Analyzer), which is accessed by JTAG interface. This is very practical, but it is intended for debug only. What if...
Choosing a mail server solution

Choosing a mail server solution

Choosing a mail server solution Having your own domain mail address sounds definitely better than using 3rd party service such as @outlook.com or yahoo.com. This however comes at a price as you have to either pay for a hosted mail services or run your own mail server....
Scrambling and Descrambling Example

Scrambling and Descrambling Example

I was recently asked for some support regarding the usage of Scramblers and Descramblers. So far to be honest, I didn’t had much time to dig-into the scramblers and descramblers problematic, but I do know, that there are interfaces such as the Xilinx’s...
Vivado VersionControl

Vivado VersionControl

Whoever is familiar with Vivado already knows that it generates a huge quantity of files and that understanding a proper version control thus seems to be not as simple. The truth is, that Vivado’s design indeed consist of a plenty of different file types, but...
Accessing physical memory from user space

Accessing physical memory from user space

I have noticed, that there are plenty of people, who do not know how to access the physical memory from Linux (or for myself at least from Xilinx’s petalinux). Basically, a bare-metal application running on a CPU has direct access to memory by default, but...