Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks, Filters, FFTs and other parts of some complex signal processing IPs. Checking whether they work as intended and that the DSP block doesn’t create any artifacts such as underflows or overflows. For this purpose, the Mathwork’s simulink block could be used as its a great tool for simulation as well (One can compile the simulink model into an IP as well). But what if we have some complex RTL- based IP, that’s needs to be verified by some long data sequence?

In that case, it might not be a bad idea is to create this sequence somewhere outside the simulator, save it to a .txt, feed the IP with these data and then save the results back to a .txt for further processing, for example, Matlab , Octave, Python or C/C++ would do just fine. One should however has to take extra care, if the data in the .txt file are representable in the testbench, which uses these data. Eg. one of mistakes was to use 32768 in 2’S complement format Q16.15 (Where the maximum is defined as 0x7FFF -> 32767). 


Tip: Saved data may be loaded to Matlab via “load(‘filename.txt’)“.
Tip: Data sequence may be generated by “printf(“%d\n”)