There are many possibilities of how you might debug your FPGA design. The most straigtforward way is to use the Chipscope (ILA – Integrated Logic Analyzer), which is accessed by JTAG interface. This is very practical, but it is intended for debug only. What if you want to configure a part of your design and optionally debug it as well? Users of SoC devices such as Zynq have the option to usually quite easily prepare a bootable image via petalinux / RTOS and issue the necessary commands to the FPGA fabric through any of the AXI_M interfaces available on the processing system. 

If you do however only have an FPGA, you dont have such option. You can use the Microblaze / Nios Softcore processors and run some form of application on these for sure, but this requires additional effort and FPGA resources. The other option is to interface to the outer world via a UART / SPI interface or in advanced cases through interfaces such as PCIe. If you want to quickly build a design and do not require some intense configuration writes, then PCIe is not a good option . What comes quite handy is the JTAG to AXI Master IP.

This IP converts the JTAG traffic to AXI4/AXI4L traffic, so that you can use it as a master for your entire AXI4 infrastructure. The only thing you need is to provide a reset and a clock, thats basically all. The minimum diagram is shown below (PDF here). So if you have ever wondered how to light-up a LED on your board (My favorite task), here is the answer. After programming the device, you have to connect via JTAG and just issue AXI4/AXI4L transactions via TCL. Advanced users can of course implement a full TCL – based DMA framework :-) 

If you want, you can of course use the JTAG2AXI Master IP only and get rid of the IP-integrator (Dont forget to assign an address for your slaves in the address editor in case you use it) and build your custom AXI4/AXI4L slave IP. This would be actually the minimal setup. After we are done with programming, here follows the TCL scripting part (From vivado TCL console):

Note: For heavy-duty tests and debugging, it may be convenient to read results from FPGA and write them to a file for offline analysis (via Matlab for example) :

TIP: You may use the ‑queue option for run_hw_axi in order to improve performance of the transfer (In case the IP is configured to support queue ).I do also recommend to add the -quiet option to the same command since it forbids the creation of additional messages in Vivado, which slightly improves performance as well. The JTAG to AXI IP may also be instantiated several times, which may comes handy as no additional AXI4/AXI4L interconnect is required. You would only access those via [get_hw_axis hw_axi_1] & [get_hw_axis hw_axi_2].

Additional good source of information about tcl usage is located in the UG835.

Additional information may be found in the IP guide (PG174) or in UG908 – Vivado Design Suite “Programming and Debugging”. Dont forget to use the docnav to always find the latest version of the associated documents! By the way: I did have 2 leds in my design Red and Green. I dont like red too much, but decided to connect it as well. They are on address 0x8008004 and use the two LSBs (theas why i issue 0x00000003). I do also have a Read-Only random magic value on address 0x80080000 of “7B8177AF” to verify the function of the interface “just in case”. And yes,I do have the most cost-optimized FPGA on the market (xc7z007s – Minized) and of course, you can use JTAG even for Zynq, although this doesnt make much sense O:)