T his post continues with the kernel driver development of “advanced” examples of AXI Timer and AXI DMA . In fact, they are no as advanced as they could be, though they should be sufficient to begin with. A more advanced usage would be the Scatter-Gather (SG) mode or a Cyclic mode or even a full customized RTL code with its own drivers. Nevertheless, writing an RTL trigger or timer is not as hard. Furthermore, its always a good idea to have a reference when in doubt. A good reference might be Xilinx DMA drivers on github.
Note: This post was originally password-protected, but in the end (Late 2021), I have decided to remove the protection 😇 Thank you for your support and have fun reading and coding!
Now that we know how to build a kernel module, lets see how to implement an interrupt handler. For this purpose,we are going to use the mentioned AXI Timer IP core from Xilinx. The simplest option to use it is to instantiate the component in the IP Integrator (Block Diagram) containing already the PS-part of the processor (Either Zynq or ZynqMP processing system). We do need to access the AXI4-L interface of the IP as well as to route the interrupt line into the PS. The IRQ_F2P port needs to be enabled in the IP configuration to allow the PL to interrupt the PS. The IP Integrator’s Address map needs to assign the AXI4-L address range for the timer either through GP_0 or GP_1 (For Zynq7000). The Choice is irrelevant as is the address. The address range must comply with the IP requirements. The minimum working scheme is shown below (pdf here): It is important to note the concat block, which by default uses “auto” width for all ports. I HIGHLY recommend to not do this and specify instead manually the width of each port of the concat IP. The reason is, that if you connect your interrupt so that there will be some unused ports (IE to your interrupt uses index 3, but index 2 is unused and configured to auto), then you are likely going to have a headache if you will modify the device tree by yourself and not by the tool. Because the tool knows that index 2 is unused and connects your interrupt to port 2 instead of port 3. Therefore manually specifying in DeviceTree to use port 3 will never work. Before we dwell into interrupt handler and DeviceTree, lets see how interrupts are defined there: This is the most important number, double check it always. Lookup the corresponding TRM and find the Interrupt mappings into the GIC (Generic Interrupt Controller). You will find that: IRQPF2P[7:0] maps to [68:61] and IRQPF2P[15:8] maps to [91:84] (For Zynq7000). These Before moving onto the DT, one last important thing: The Interrupt handler we are going to write later on MUST clear the interrupt flag.
Lets see how the overall device tree entry looks like for the AXI Timer:
Whats is most important: Again, the Interrupt identification and the “compatible” node, which says,which driver is compatible with the device. I did manually modified the default value (compatible = “xlnx,axi-timer-2.0″, “xlnx,xps-timer-1.00.a“;) to “xlnx,beechwood-irq-driver” so that the xilinx’s driver for their core is not used (The kernel will not know what driver to use for the DT node until we load our module). Also note the “reg” property, which defines at which address is the AXI4-L interface located. For this example, I have chosen 0x80020000, which is GP1 port of the Zynq PS (Yes, unlike in the previous picture) and has a dedicated range of 64KB (0x10000). Do not however try to load the device driver in case the memory address is not accessible (until the FPGA is programmed with the AXI Timer bitstream) – the system will freeze. Other node properties are not extra important for us. You could remove the clocking section completely, as we not going to disable/enable/change the clock frequencies upon loading/removal of the kernel driver. I have tried to make the code as self-explanatory, as possible, but anyway, the most important things. The module uses the platform drivers. Among the code, most important part is the table, which defines the compatibility options. Upon loading the driver, the kernel goes through the device tree and tries to find a compatible node, which in our case is the “beechwood-irq-driver“. The module must have a “probe” and “remove” functions associated. In the probe function, we register the interrupt handler by looking at the corresponding device tree node (irq_of_parse_and_map and request_irq functions). After registering the interrupt handler routine, we configure the AXI Timer to generate interrupts. In this example,I have chosen the interrupt period to be 0.25sec based on the frequency the timer is running on. This in my case is the FCLK_CLK0 PL fabric clock, which needs to have a frequency of 100MHz. Here comes the part that you should know how the FSBL has configured your platform in order to have this period. In case the period differs, then the FCLK0 clock is different than 100 MHz. The code that setups the period is based on PG079. A small hint here: The Xilinx’s timer generates an interrupt on the overflow of the 32b counter. Therefore you have to properly adjust the load value so that the overflow will occur in the required time (0.25s).
Upon successful module compilation, FPGA programming with a new bitstream, modification of the DeviceTree and insertion of the module, you should see a kernel log via dmesg similar to the following output (Note that the timestamp differences should be 0.25sec). Important note: Make sure the interrupt gets cleared in the handler. If not, then interrupts will be generated continuously (for level sensitive interrupt definition) so that the system will freeze! Also don’t forget to unregister the interrupt handler in the “remove” function. Congratulations! Now we are able to use the AXI Timer, modify the FPGA, DeviceTree and register some interrupts.AXI Timer with simple IRQ Handler
Interrupt definition (X):
Interrupt sensitivity (Z):
Interrupt Line (Y):
“are” the numbers you are looking for. Well only in case if you specify the interrupts as SPI [1]. The truth is however that they are not shared, so that you have to specify 0 for them. As a result, the correct interrupt identification is “-32”. IE: IRQF2P[7:0] maps NOT to [68:61], but [36:29], 29 being the pl index 0. The Vivado tool and flow handles this for you, but in case you want to write it for yourself, you have to take care.
DMA With Interrupt and Cache Coherency
In order to play with a DMA and transfer some pseudo random bytes on 100MHz clock, lets say a few notes before: For simplicity, we are going to use the AXI DMA IP (PG021), both S2MM and MM2S channels and only in Direct register mode. This simplifies the “testbench” as using Scatter-Gather would be more complicated. Furthermore, we assume that the S_AXI_HP0 port has a pre-configured width of 32b by the FSBL (Zynq has options to support 32b/64b. ZynqMP also supports 128b width). If we would use the hardware cache coherency ports (S_AXI_ACP for Zynq7000 and or S_AXI_HPC[0:1] for ZynqMP), we wouldn’t also need to worry about coherency and just write some basic user-space driver for the DMA, but because the intention is to not make things so simple, we will use the S_AXI_HP0 port of the Zynq PS. Lets start with the IP Integrator (pdf here):
Shown is the simplest diagram we can use. There is one AXI4 interconnect for the DMA’s AXI4-L interface connected to GP0 and another AXI4 interconnect before the S_AXI_HP0 port (Make sure your platform was initialized with the correct bitwidth – this would otherwise cause problems). All the clocks are synchronous in the design and the S2MM (Stream to Memory) and MM2S (Memory to Stream) interrupts are routed to the IRQ_F2P ports with indexes 0 and 1. What is not shown however in this diagram is how the S2MM and MM2S streams interact. This is external to the diagram and basically there is an additional Xilinx FIFO and a simple RTL code, which increments each incoming 32b word by 1:
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---------------------------------------------------------- ------- Testing Cache Coherency inside Linux Kernel ------ process(PL1_Clk) begin if rising_edge(PL1_Clk) then HP_MM2S_Data_Vld_Reg <= HP_MM2S_tvalid; HP_MM2S_Data_Tlast_Reg <= HP_MM2S_tlast; HP_MM2S_Data_Reg <= std_logic_vector(unsigned(HP_MM2S_tdata) + 1); end if; end process; CacheFIFO:HP_DMA_FIFO port map( wr_rst_busy => open, rd_rst_busy => open, s_aclk => PL1_Clk, s_aresetn => HP_MM2S_RSTN, s_axis_tready => open, s_axis_tvalid => HP_MM2S_Data_Vld_Reg, s_axis_tdata => HP_MM2S_Data_Reg, s_axis_tlast => HP_MM2S_Data_Tlast_Reg, m_axis_tvalid => HP_S2MM_tvalid, m_axis_tready => HP_S2MM_tready, m_axis_tdata => HP_S2MM_tdata, m_axis_tlast => HP_S2MM_tlast, axis_prog_full => CacheCo_FIFO_FULL ); HP_MM2S_tready <= not CacheCo_FIFO_FULL; HP_S2MM_tkeep <= (others => '1'); |
As you can see, the FIFO is there only because I didn’t wanted to bother myself with proper handling of the tready signaling, so that instead a threshold of 500 out of 512 samples is considered a criterion when tready get deasserted for the MM2S. Anyway, its worth to mention that when an AXI DMA MM2S channel is reset, the reset is propagated into the FIFO (mm2s_rst_n and s2mm_rst_n signals). This is a good practice to reset the FIFO before starting additional transfers. For some application,it might be necessary to use FIFOs for both channels. However 1 FIFO is sufficient here. Now that we have the RTL ready, lets move onto the device tree:
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// ---------------------------------------------------------------------- // ------ PL AXI DMA Connected to Zynq HP0 Port (Custom Modified) ------- HP_RW_DMA: HP_RW_DMA_0@80400000 { clock-frequency = <100000000>; // Clock Frequency clock-names = "s_axi_aclk"; // Clock Name clocks = <&clkc 16>; // Clock ID compatible = "xlnx,beechwood-dma-driver"; // Compatible Driver interrupt-names = "mm2s_int","s2mm_int"; // Interrupt names interrupt-parent = <&intc>; // Interrupt Parent interrupts = <0 31 4>,<0 32 4>; // Interrupt IDs | Level Sensitive reg = <0x80400000 0x10000>; // AXI4L Base Address + Address Range xlnx,addrwidth = <0x20>; // 32b Address Width }; |
The reg property is as always based on the IP integrator’s address editor and this time represents the GP_1 port of the Zynq PS. Also the interrupt numbers are not identical to the picture provided. Correct would be to use <0 29 4>,<0 30 4>. The Reg property is useful in case we are going to parse the address from a device tree. In that case platform_get_resource and devm_ioremap_resource functions could be used. Since we however know the exact addresses (Well in fact also the interrupt numbers), the reg property is not of extra use for us and we can just use request_mem_region and ioremap_nocache. In fact writing an entire driver without the devicetree modification is an option, but its somewhat convenient to make the kernel module parse the parameters and modify any settings in the DT thereafter. Whats important is again the compatible property, which is set to “xlnx,beechwood-dma-driver“. This can be really an arbitrary string as long as the node matches the compatible property value in the module table.
I have also used an LCG generator in order to generate some pseudo random data and verify that there are no issues with the coherency and transfers (This is a PRN sequence generator, once data are generated with a seed, we can regenerate them again using the same seed – this is used in the code with the following command: Seed = Seed_Orig;). Quite obviously, we also need 2 buffers to for RD and WR operations (Well theoretically a single buffer could as well be used for this purpose). The reset sequence of the DMA channels doesn’t matter, but I do recommend to start the channels in the following order: (S2MM and then MM2S). This way, you can be sure, that when data are coming from MM2S, the S2MM should be ready to accept them, since it has been configured previously and waits for valid transfers. Also there are 2 separate Interrupt handlers for the channels. Since the correct usage of Interrupts wasnt the goal of this exercise, they just mirror the “Polling” mechanism (which is by default omitted using IFDEF macros) and the only thing they does is that they clear the interrupt flags of the AXI DMA. The most important thing is however the following piece of code:
- dma_alloc_coherent
This function actually uses the DMA framework and guarantees that any CPU accesses to the allocated region are considered as “cache miss” – therefore accessing directly the memory region. On the other hand, this also implies that accesses to this memory are costly. It is however necessary for DMA operations to allocate the memory this way. The correct usage of AXI DMA is all based on the PG021 document. Additional information on controlling the DMA may be found here: Lauri’sBlog. Additional note on the configuration: CHAN_CR_IOC_IrqEn is the required flag in order for the DMA to trigger the interrupt. CHAN_CR_Err_IrqEn is optional.
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#include <linux/bitops.h> #include <linux/platform_device.h> #include <linux/init.h> #include <linux/types.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/dma-mapping.h> #include <linux/dmapool.h> // Dma alloc coherent #include <linux/io-64-nonatomic-lo-hi.h> #include <linux/kernel.h> // dma_addr_t #include <linux/delay.h> // Sleep #include <linux/spinlock.h> // Spinlock #include <linux/of_address.h> #include <linux/of_dma.h> #include <linux/of_platform.h> #include <linux/of_irq.h> #include <linux/random.h> // --------------------------------- // ------- AXI DMA Registers ------- #define DMA_BASE (0x80400000) // AXI4L Base Address #define DMA_REGION (65536) // Amount of Bytes for AXI4L Range #define DMA_MAX_BYTES 8192 // Maximum Transfer Size #define MM2S_DMACR (0x00000000) // MM2S Direct Register Mode #define MM2S_DMASR (0x00000004) // MM2S Direct Register Mode #define MM2S_SA_LSB (0x00000018) // MM2S Direct Register Mode #define MM2S_SA_MSB (0x0000001C) // MM2S Direct Register Mode #define MM2S_LENGTH (0x00000028) // MM2S Direct Register Mode #define S2MM_DMACR (0x00000030) // S2MM Direct Register Mode #define S2MM_DMASR (0x00000034) // S2MM Direct Register Mode #define S2MM_DA_LSB (0x00000048) // S2MM Direct Register Mode #define S2MM_DA_MSB (0x0000004C) // S2MM Direct Register Mode #define S2MM_LENGTH (0x00000058) // S2MM Direct Register Mode #define CHAN_CR_START (1 << 0) // 1 Starts || 0 Stops #define CHAN_CR_ONE (1 << 1) // Reads as One #define CHAN_CR_RESET (1 << 2) // Reset of the DMA #define CHAN_CR_IOC_IrqEn (1 << 12) // IOC Interrupt Enable #define CHAN_CR_Dly_IrqEn (1 << 13) // DLY Interrupt Enable #define CHAN_CR_Err_IrqEn (1 << 14) // ERR Interrupt Enable #define CHAN_SR_HALTED (1 << 0) // 0 == Running | 1 == Halted #define CHAN_SR_IDLE (1 << 1) // 0 == Not Idle | 1 == IDLE #define CHAN_SR_INT_ERR (1 << 4) // Internal Error #define CHAN_SR_SLV_ERR (1 << 5) // Slave Error #define CHAN_SR_DEC_ERR (1 << 6) // Decode Error #define CHAN_SR_IOC_IRQ (1 << 12) // Interrupt on Complete W1C #define CHAN_SR_DLY_IRQ (1 << 13) // Interrupt on Delay W1C #define CHAN_SR_ERR_IRQ (1 << 14) // Interrupt on Error W1C struct dma_channel_t{ int Channel_Flag; // Flag For Completion int Channel_IRQ; // IRQ Number spinlock_t Channel_Lock; // Channel Locking for Sharing Data void __iomem *regs; // AXI4L Registers for entire DMA }; /************************************************************************* * This is acustom driver structure,which should use the * platform_set_drvdata(pdev,config) & config = platform_get_drvdata(pdev) * NOTE: Any driver-specific information goes here ************************************************************************/ struct beechwood_dma_structure{ struct resource* MemRegion; // Memory Region struct device *dev; // Device Structure struct device_node *node; // Device Tree Spec void __iomem *regs; // FPGA AXI4-L Registers struct dma_channel_t *MM2S; // MM2S DMA Channel struct dma_channel_t *S2MM; // S2MM DMA Channel dma_addr_t Buff_Physical0; // Buffer #0 - Source Physical Address dma_addr_t Buff_Physical1; // Buffer #1 - Destination Physical Address unsigned int *Buff_Virt_0; // Buffer #0 - Source Virtual Address unsigned int *Buff_Virt_1; // Buffer #1 - Destination Virtual Address unsigned int BufferSize_Bytes; // Buffer Bytes unsigned int BufferSize_Words; // Buffer 32b Words }; /************************************************************************** * Beechwood Interrupt S2MM DMA handler * @irq : IRQ number same as in request_irq(); * @data : Same as in request_irq(); * Return: IRQ_HANDLED/IRQ_NONE **************************************************************************/ static irqreturn_t DMA_S2MM_Interrupt_handler(int irq, void *data){ struct dma_channel_t *channel_config; unsigned int RegValue; unsigned int IntMask; // ---------------------------------- // ------- Reassign Structure ------- channel_config = (struct dma_channel_t*)data; IntMask = CHAN_SR_IOC_IRQ | CHAN_SR_DLY_IRQ | CHAN_SR_ERR_IRQ; RegValue = ioread32(channel_config->regs + S2MM_DMASR); printk(KERN_INFO "Calling S2MM Handler with IRQ: %d\n",irq); // ------------------------------------------------- // ------- Check if this is the right handler ------ if (!(RegValue & IntMask)){return IRQ_NONE;} // ----------------------------------------------- // ------- Clear S2MM_DMASR Interrupt Flags ------ RegValue = IntMask; // Most values are Read Only iowrite32(RegValue, channel_config->regs + S2MM_DMASR); printk(KERN_INFO "S2MM Interrupt Handler!\n"); if(RegValue & CHAN_SR_INT_ERR){printk(KERN_ERR "S2MM DMA Internall Error!\n");} if(RegValue & CHAN_SR_SLV_ERR){printk(KERN_ERR "S2MM DMA Slave Error!\n");} if(RegValue & CHAN_SR_DEC_ERR){printk(KERN_ERR "S2MM DMA Decode Error!\n");} // --------------------------------- // ------ Mark Flag Finished ------- spin_lock(&channel_config->Channel_Lock); channel_config->Channel_Flag = 1; spin_unlock(&channel_config->Channel_Lock); return IRQ_HANDLED; } /************************************************************************** * Beechwood Interrupt S2MM DMA handler * @irq : IRQ number same as in request_irq(); * @data : Same as in request_irq(); * Return: IRQ_HANDLED/IRQ_NONE **************************************************************************/ static irqreturn_t DMA_MM2S_Interrupt_handler(int irq, void *data){ struct dma_channel_t *channel_config; unsigned int RegValue; unsigned int IntMask; // ---------------------------------- // ------- Reassign Structure ------- channel_config = (struct dma_channel_t*)data; IntMask = CHAN_SR_IOC_IRQ | CHAN_SR_DLY_IRQ | CHAN_SR_ERR_IRQ; RegValue = ioread32(channel_config->regs + MM2S_DMASR); printk(KERN_INFO "Calling MM2S Handler with IRQ: %d \n",irq); // ------------------------------------------------- // ------- Check if this is the right handler ------ if (!(RegValue & IntMask)){return IRQ_NONE;} // ----------------------------------------------- // ------- Clear MM2S_DMASR Interrupt Flags ------ RegValue = IntMask; // Most values are Read Only iowrite32(RegValue, channel_config->regs + MM2S_DMASR); printk(KERN_INFO "MM2S Interrupt Handler!\n"); if(RegValue & CHAN_SR_INT_ERR){printk(KERN_ERR "MM2S DMA Internall Error!\n");} if(RegValue & CHAN_SR_SLV_ERR){printk(KERN_ERR "MM2S DMA Slave Error!\n");} if(RegValue & CHAN_SR_DEC_ERR){printk(KERN_ERR "MM2S DMA Decode Error!\n");} // ----------------------------- // ------- Mark Finished ------- spin_lock(&channel_config->Channel_Lock); channel_config->Channel_Flag = 1; spin_unlock(&channel_config->Channel_Lock); return IRQ_HANDLED; } /******************************************************** *@brief Resets the Direct Register Mode DMA S2MM Channel ********************************************************/ void DMA_Direct_S2MM_Reset(void *Regs, unsigned int Timeout_ms){ unsigned int RegValue; unsigned int Timeout_Cnt_ms; unsigned int IntMask; // --------------------------------- // ------- SOFT RESET THE DMA ------ RegValue = (CHAN_CR_RESET); IntMask = CHAN_SR_IOC_IRQ | CHAN_SR_DLY_IRQ | CHAN_SR_ERR_IRQ; iowrite32(IntMask,Regs + S2MM_DMASR); // Reset Interrupts iowrite32(RegValue,Regs + S2MM_DMACR); // Reset Channel Timeout_Cnt_ms = 0; while(1){ RegValue = ioread32(Regs + S2MM_DMACR); if((RegValue & CHAN_CR_RESET) == 0){ break; } msleep(1); Timeout_Cnt_ms = Timeout_Cnt_ms +1; if(Timeout_Cnt_ms > Timeout_ms){ printk(KERN_ERR "Error S2MM DMA Reset Timeout\n"); break; } } } /******************************************************** *@brief Resets the Direct Register Mode DMA S2MM Channel ********************************************************/ void DMA_Direct_MM2S_Reset(void *Regs,unsigned int Timeout_ms){ unsigned int RegValue; unsigned int Timeout_Cnt_ms; unsigned int IntMask; // --------------------------------- // ------- SOFT RESET THE DMA ------ RegValue = (CHAN_CR_RESET); IntMask = CHAN_SR_IOC_IRQ | CHAN_SR_DLY_IRQ | CHAN_SR_ERR_IRQ; iowrite32(IntMask,Regs + MM2S_DMASR); // Reset Interrupts iowrite32(RegValue,Regs + MM2S_DMACR); // Reset Channel Timeout_Cnt_ms = 0; while(1){ RegValue = ioread32(Regs + MM2S_DMACR); if((RegValue & CHAN_CR_RESET) == 0){ break; } msleep(1); Timeout_Cnt_ms = Timeout_Cnt_ms +1; if(Timeout_Cnt_ms > Timeout_ms){ printk(KERN_ERR "Error MM2S DMA Reset Timeout\n"); break; } } } /********************************************************* *@brief Starts the DMA With Destination Address Specified *********************************************************/ void DMA_Direct_S2MM_Start(void *Regs,dma_addr_t Dest_Addr,unsigned int Bytes){ unsigned int Addr_LSB; unsigned int Addr_MSB; unsigned int RegValue; unsigned int Interrupts; if(Bytes > DMA_MAX_BYTES){ printk(KERN_ERR "Error: S2MM DMA: Too big Transfer Size!\n"); return; } Addr_LSB = lower_32_bits(Dest_Addr); //(uint32_t)((Dest_Addr & 0x00000000FFFFFFFF) >> 0); Addr_MSB = upper_32_bits(Dest_Addr); //(uint32_t)((Dest_Addr & 0xFFFFFFFF00000000) >> 32); printk(KERN_INFO "Starting S2MM DMA With Destination Address: 0X%08X\n",Addr_LSB); printk(KERN_INFO "Starting S2MM DMA With Amount of %d Bytes\n",Bytes); // ---------------------- // -------- HALT -------- RegValue = 0x00000000; iowrite32(RegValue,Regs + S2MM_DMACR); // ------------------------------------------ // ------- WRITE Destination Address ------- iowrite32(Addr_MSB,Regs + S2MM_DA_MSB); iowrite32(Addr_LSB,Regs + S2MM_DA_LSB); // ------------------------------------------------ // ------- START DMA WITH INTERRUPTS ENABLED ------ // Note: DLY and Threshold are not used for direct register access Interrupts = (CHAN_CR_IOC_IrqEn);// | CHAN_CR_Err_IrqEn); // Enable Interrupt RegValue = ioread32(Regs + S2MM_DMACR); // Read Default RegValue |= (CHAN_CR_START | Interrupts); // Start the Channel iowrite32(RegValue,Regs + S2MM_DMACR); // Write the Settings // ----------------------------------------------- // ------ CHECK THAT THE CHANNEL IS RUNNING ------ RegValue = ioread32(Regs + S2MM_DMASR); if((RegValue & CHAN_SR_HALTED) == CHAN_SR_HALTED){ printk(KERN_ERR "Error S2MM DMA Channel Not Running!\n"); } // --------------------------- // ------- SETUP LENGTH ------ iowrite32(Bytes,Regs + S2MM_LENGTH); } /********************************************************* *@brief Starts the DMA With Source Address Specified *********************************************************/ void DMA_Direct_MM2S_Start(void *Regs,dma_addr_t Source_Addr,unsigned int Bytes){ unsigned int Addr_LSB; unsigned int Addr_MSB; unsigned int RegValue; unsigned int Interrupts; if(Bytes > DMA_MAX_BYTES){ printk(KERN_ERR "Error: MM2S DMA: Too big Transfer Size!\n"); return; } Addr_LSB = lower_32_bits(Source_Addr); Addr_MSB = upper_32_bits(Source_Addr); printk(KERN_INFO "Starting MM2S DMA With Source Address: 0X%08X\n",Addr_LSB); printk(KERN_INFO "Starting MM2S DMA With Amount of %d Bytes\n",Bytes); // ---------------------- // -------- HALT -------- RegValue = 0x00000000; iowrite32(RegValue,Regs + MM2S_DMACR); // ------------------------------------- // ------- WRITE Source Address ------- iowrite32(Addr_MSB,Regs + MM2S_SA_MSB); iowrite32(Addr_LSB,Regs + MM2S_SA_LSB); // ------------------------------------------------ // ------- START DMA WITH INTERRUPTS ENABLED ------ // Note: DLY and Threshold are not used for direct register access Interrupts = (CHAN_CR_IOC_IrqEn); // | CHAN_CR_Err_IrqEn); // Enable Interrupt RegValue = ioread32(Regs + MM2S_DMACR); // Read Default RegValue |= (CHAN_CR_START | Interrupts); // Start the Channel iowrite32(RegValue,Regs + MM2S_DMACR); // Write the Settings // ----------------------------------------------- // ------ CHECK THAT THE CHANNEL IS RUNNING ------ RegValue = ioread32(Regs + MM2S_DMASR); if((RegValue & CHAN_SR_HALTED) == CHAN_SR_HALTED){ printk(KERN_ERR "Error MM2S DMA Channel Not Running!\n"); } // --------------------------- // ------- SETUP LENGTH ------ iowrite32(Bytes,Regs + MM2S_LENGTH); } /********************************************* * @brief Wait for DMA to finish its transfer *********************************************/ void DMA_Direct_S2MM_Wait_Poll(void *Regs, unsigned int Timeout_ms){ unsigned int RegValue; unsigned int Timeout_Cnt_ms; unsigned int BytesTransfered; Timeout_Cnt_ms = 0; while(1){ RegValue = ioread32(Regs + S2MM_DMASR); if(RegValue & CHAN_SR_INT_ERR){printk(KERN_ERR "S2MM DMA Internal Error!\n");} if(RegValue & CHAN_SR_SLV_ERR){printk(KERN_ERR "S2MM DMA Slave Error!\n");} if(RegValue & CHAN_SR_DEC_ERR){printk(KERN_ERR "S2MM DMA Decode Error!\n");} if((RegValue & CHAN_SR_IOC_IRQ) || (RegValue & CHAN_SR_IDLE)){ printk(KERN_INFO "S2MM DMA Done in %d ms\n",Timeout_Cnt_ms); break; } if(Timeout_Cnt_ms > Timeout_ms){ printk(KERN_ERR "Error S2MM DMA Timeout\n"); break; } msleep(1); Timeout_Cnt_ms ++; } BytesTransfered = ioread32(Regs + S2MM_LENGTH); printk(KERN_INFO "S2MM Bytes Transfered: %d \n",BytesTransfered); } /********************************************* * @brief Wait for DMA to finish its transfer *********************************************/ void DMA_Direct_MM2S_Wait_Poll(void *Regs,unsigned int Timeout_ms){ unsigned int RegValue; unsigned int Timeout_Cnt_ms; unsigned int BytesTransfered; Timeout_Cnt_ms = 0; while(1){ RegValue = ioread32(Regs + MM2S_DMASR); if(RegValue & CHAN_SR_INT_ERR){printk(KERN_ERR "MM2S DMA Internall Error!\n");} if(RegValue & CHAN_SR_SLV_ERR){printk(KERN_ERR "MM2S DMA Slave Error!\n");} if(RegValue & CHAN_SR_DEC_ERR){printk(KERN_ERR "MM2S DMA Decode Error!\n");} if((RegValue & CHAN_SR_IOC_IRQ) || (RegValue & CHAN_SR_IDLE)){ printk(KERN_INFO "DMA Done in %d us\n",Timeout_Cnt_ms); break; } if(Timeout_Cnt_ms > Timeout_ms){ printk(KERN_ERR "Error DMA Timeout\n"); break; } msleep(1); Timeout_Cnt_ms ++; } BytesTransfered = ioread32(Regs + MM2S_LENGTH); printk(KERN_INFO "MM2S Bytes Transfered: %d \n",BytesTransfered); } /**************************************************************** *@brief Utilizes the Xilinx's AXI DMA Direct Register Access DMA ****************************************************************/ void DMAX_Transfer(void *Regs,dma_addr_t Source,dma_addr_t Dest,unsigned int Bytes,struct beechwood_dma_structure *driver_config){ unsigned int Timeout_ms = 10; unsigned int RegValue_S2MM; unsigned int RegValue_MM2S; unsigned int Timeout_Cnt_ms; unsigned long int S2MM_Flags; unsigned long int MM2S_Flags; RegValue_S2MM = ioread32(Regs + S2MM_DMACR); RegValue_MM2S = ioread32(Regs + MM2S_DMACR); if((RegValue_S2MM & CHAN_CR_ONE) != CHAN_CR_ONE){ printk(KERN_INFO "Error S2MM DMA Probe Failed!\n"); return; } if((RegValue_MM2S & CHAN_CR_ONE) != CHAN_CR_ONE){ printk(KERN_INFO "Error MM2S DMA Probe Failed\n"); return; } // ------------------------ // ------ Reset MM2S ------ printk(KERN_INFO "Begin Reset MM2S\n"); DMA_Direct_MM2S_Reset(Regs,Timeout_ms); // ------------------------- // ------ Reset S2MM ------- printk(KERN_INFO "Begin Reset S2MM\n"); DMA_Direct_S2MM_Reset(Regs,Timeout_ms); // ------------------------------------------------ // ------ Clear flags for Interrupt Handlers ------ driver_config->S2MM->Channel_Flag = 0; driver_config->MM2S->Channel_Flag = 0; // ------------------------ // ------ Setup S2MM ------ printk(KERN_INFO "Starting S2MM\n"); DMA_Direct_S2MM_Start(Regs,Dest,Bytes); // -------------------------- // ------- Setup MM2S ------- printk(KERN_INFO "Starting MM2S \n"); DMA_Direct_MM2S_Start(Regs,Source,Bytes); #if 0 // ------------------------------------------------------------------------------ // ------ This section could be used if the Interrupts are not registered ------- // ------------------------- // ------- WAIT MM2S ------- printk(KERN_INFO "Waiting MM2S\n"); DMA_Direct_MM2S_Wait_Poll(Regs,Timeout_ms); // ------------------------- // ------- WAIT S2MM ------- printk(KERN_INFO "Waiting S2MM\n"); DMA_Direct_S2MM_Wait_Poll(Regs,Timeout_ms); #else // ------------------------------------------------------------------ // ------ Manual Waiting for the Interrupt Handler to Complete ------ Timeout_Cnt_ms = 0; while(1){ msleep(1); Timeout_Cnt_ms ++; // ----------------------------------------------------- // ------- Check that the Interrupts are finished ------ spin_lock_irqsave(&driver_config->S2MM->Channel_Lock, S2MM_Flags); spin_lock_irqsave(&driver_config->MM2S->Channel_Lock, MM2S_Flags); if((driver_config->MM2S->Channel_Flag == 1) && (driver_config->S2MM->Channel_Flag == 1)){ printk(KERN_INFO "S2MM & MM2S Interrupts Complete!\n"); spin_unlock_irqrestore(&driver_config->S2MM->Channel_Lock, S2MM_Flags); spin_unlock_irqrestore(&driver_config->MM2S->Channel_Lock, MM2S_Flags); break; } spin_unlock_irqrestore(&driver_config->S2MM->Channel_Lock, S2MM_Flags); spin_unlock_irqrestore(&driver_config->MM2S->Channel_Lock, MM2S_Flags); if(Timeout_Cnt_ms > Timeout_ms){ printk(KERN_ERR "Error DMA Timeout\n"); break; } } #endif } /*************************************************************** * Linear Congruential Generator based on minstd_rand C++ 11 * https://en.wikipedia.org/wiki/Linear_congruential_generator ***************************************************************/ int LCG_Gen(int x,int m,int a,int c){ int Res; Res = (a*x + c) % m; return Res; } /*************************************************************************************************** * ---------------------------------------------------------------- * ------- ------- DMA Coherency Playing & Allocation ----- ------- * In order for the DMA Api to work,there needs to be reserved space for DMA inside the DT. * The DMA API Automatically Flushes / Invalidates the CPU Read/Writes * void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag) ************************************************************************************************/ static int beechwood_dma_probe(struct platform_device *pdev){ unsigned int i; // Indexing unsigned int j; // Indexing unsigned int NumErr_10; // Amount of Errors | Direction 1 --> 0 unsigned int NumErr_01; // Amount of Errors | Direction 0 --> 1 unsigned int RegValue; // Custom Register Value unsigned int IntMask; // Interrupt masking int MM2SInterruptNumberInDT; // Interrupt Index into DT int S2MMInterruptNumberInDT; // Interrupt Index into DT int S2MM_IRQ_Err; // Interrupt Err Detection int MM2S_IRQ_Err; // Interrupt Err Detection // LCG Variables int Seed; int Seed_Orig; int a; int m; int c; // -------------------------------------------------- // ------- Main Driver Configuration Structure ------ struct beechwood_dma_structure *driver_config; printk(KERN_INFO "Beechwood DMA Probe init\n"); // ---------------------------------------------------------------------------- // Allocate Any memory if required by the Driver and its structures driver_config = devm_kzalloc(&pdev->dev, sizeof(*driver_config), GFP_KERNEL); if (!driver_config){ printk(KERN_ERR "Error beechwood DMA driver kernel allocation - out of memory \n"); return -ENOMEM; } driver_config->S2MM = devm_kzalloc(&pdev->dev, sizeof(*driver_config->S2MM), GFP_KERNEL); if (!driver_config->S2MM){ printk(KERN_ERR "Error beechwood S2MM DMA driver kernel allocation - out of memory \n"); return -ENOMEM; } driver_config->MM2S = devm_kzalloc(&pdev->dev, sizeof(*driver_config->MM2S), GFP_KERNEL); if (!driver_config->MM2S){ printk(KERN_ERR "Error beechwood MM2S DMA driver kernel allocation - out of memory \n"); return -ENOMEM; } // ---------------------------------------------------- // -------- Assign The Device Driver and DT Node------- driver_config->dev = &pdev->dev; driver_config->node = pdev->dev.of_node; // ---------------------------------------------------------- // ------- Map the IO Memory for AXI4L Register Access ------ // ------- Note: Could as well be parsed from DeviceTree driver_config->MemRegion = request_mem_region(DMA_BASE,DMA_REGION, "beechwood-dma-driver"); driver_config->regs = ioremap_nocache(DMA_BASE, DMA_REGION); if(!driver_config->regs){ printk(KERN_ERR "Error unablle to map AXI4 Lite DMA Register Space\n"); return EIO; } // ------------------------------------------------------------------------- // Setup Private Driver Data so that they are available via dev_get_drvdata // An example could be in "module remove": *dev = platform_get_drvdata(pdev); // -------------------------------------------------------------------------- platform_set_drvdata(pdev, driver_config); driver_config->BufferSize_Bytes = (unsigned int)DMA_MAX_BYTES; driver_config->BufferSize_Words = driver_config->BufferSize_Bytes / sizeof(unsigned int); driver_config->Buff_Virt_0 = (unsigned int*)dma_alloc_coherent(driver_config->dev,driver_config->BufferSize_Bytes,&driver_config->Buff_Physical0, GFP_KERNEL); driver_config->Buff_Virt_1 = (unsigned int*)dma_alloc_coherent(driver_config->dev,driver_config->BufferSize_Bytes,&driver_config->Buff_Physical1, GFP_KERNEL); if(!driver_config->Buff_Virt_0){ printk(KERN_ERR "Unable to allocate Buffer0 for DMA Cache Coherency Testing!\n"); return EIO; } if(!driver_config->Buff_Virt_1){ printk(KERN_ERR "Unable to allocate Buffer1 for DMA Cache Coherency Testing!\n"); return EIO; } // ------------------------------------------------------- // ------- Initialize Spinlock for the IRQ Handlers ------ spin_lock_init(&driver_config->S2MM->Channel_Lock); spin_lock_init(&driver_config->MM2S->Channel_Lock); driver_config->S2MM->regs = driver_config->regs; driver_config->MM2S->regs = driver_config->regs; // ------------------------------------------------------- // ------- Reset DMA Channels before requesting IRQ ------ DMA_Direct_S2MM_Reset(driver_config->regs,10); DMA_Direct_MM2S_Reset(driver_config->regs,10); IntMask = CHAN_SR_IOC_IRQ | CHAN_SR_DLY_IRQ | CHAN_SR_ERR_IRQ; RegValue = ioread32(driver_config->regs + S2MM_DMASR); if(RegValue & IntMask){ printk(KERN_ERR "S2MM Interrupt not cleared!\n"); return EIO; } RegValue = ioread32(driver_config->regs + MM2S_DMASR); if(RegValue & IntMask){ printk(KERN_ERR "MM2S Interrupt not cleared!\n"); return EIO; } // ----------------------------------------------------------------------------------------------- // ------- Optionally Obtain the Interrupt Number from DeviceTree and Assign their Handlers ------ MM2SInterruptNumberInDT = 0; // This is correct,index starts from 0 S2MMInterruptNumberInDT = 1; // This is correct,index starts from 0 driver_config->S2MM->Channel_IRQ = irq_of_parse_and_map(driver_config->node, S2MMInterruptNumberInDT); driver_config->MM2S->Channel_IRQ = irq_of_parse_and_map(driver_config->node, MM2SInterruptNumberInDT); MM2S_IRQ_Err = request_irq(driver_config->MM2S->Channel_IRQ ,DMA_MM2S_Interrupt_handler,IRQF_SHARED, "mm2s-beechwood-dma-driver", driver_config->MM2S); S2MM_IRQ_Err = request_irq(driver_config->S2MM->Channel_IRQ ,DMA_S2MM_Interrupt_handler,IRQF_SHARED, "s2mm-beechwood-dma-driver", driver_config->S2MM); printk(KERN_INFO "Obtained MM2S IRQ Number from DT: %d \n",driver_config->MM2S->Channel_IRQ ); printk(KERN_INFO "Obtained S2MM IRQ Number from DT: %d \n",driver_config->S2MM->Channel_IRQ ); // --------------------------------------------------------------------- // ------ Check for Errors on Registering the Interrupt Handlers ------- if (MM2S_IRQ_Err) { dev_err(driver_config->dev, "MM2S DMA: unable to request IRQ %d\n", driver_config->MM2S->Channel_IRQ ); return MM2S_IRQ_Err; } if (S2MM_IRQ_Err) { dev_err(driver_config->dev, "S2MM DMA: unable to request IRQ %d\n", driver_config->S2MM->Channel_IRQ ); return S2MM_IRQ_Err; } // --------------------------------- // ------- Initialize the LCG ------ get_random_bytes(&Seed, sizeof(Seed)); // Random m = 0x7FFFFFFF; // Modulus a = 48271; // Multiplier c = 0; // Increment // -------------------------------------------- // ------- Test Cache Coherency Accesses ------ for(j = 0;j < 5;j++){ Seed_Orig = Seed; // ----------------------------------------- // ------ Prepare Buffer for Writing ------- for(i = 0;i < driver_config->BufferSize_Words;i++){ Seed = LCG_Gen(Seed,m,a,c); driver_config->Buff_Virt_1[i] = Seed; // Source Buffer driver_config->Buff_Virt_0[i] = 0x0; // Destination Buffer } // --------------------------------------------------- // ------ Launch MM2S & S2MM DMA FPGA Transfers ------ // Direction Buffer 1 --> Buffer 0 DMAX_Transfer(driver_config->regs, driver_config->Buff_Physical1,driver_config->Buff_Physical0,driver_config->BufferSize_Bytes,driver_config); // ---------------------------------------------- // ------ CHECK THAT THE TRANSFER WAS OKAY ------ // Note: During the transfer,each DMA WORD (32b) is incremented by 1 in VHDL. NumErr_10 = 0; Seed = Seed_Orig; for(i = 0;i < driver_config->BufferSize_Words;i++){ Seed = LCG_Gen(Seed,m,a,c); if(driver_config->Buff_Virt_0[i] != (Seed + 1)){ NumErr_10++; } } // ----------------------------------------------------- // ------- Launch MM2S & S2MM DMA FPGA Transfers ------- // Direction Buffer 0 --> Buffer 1 DMAX_Transfer(driver_config->regs, driver_config->Buff_Physical0,driver_config->Buff_Physical1,driver_config->BufferSize_Bytes,driver_config); // ---------------------------------------------- // ------ CHECK THAT THE TRANSFER WAS OKAY ------ // Note: During the transfer,each DMA WORD (32b) is incremented by 1 in VHDL. NumErr_01 = 0; Seed = Seed_Orig; for(i = 0;i < driver_config->BufferSize_Words;i++){ Seed = LCG_Gen(Seed,m,a,c); if(driver_config->Buff_Virt_1[i] != (Seed + 2)){ NumErr_01++; } } // ------------------------------------ // ------- Display Testing Info ------- printk(KERN_INFO "Loop %d (Buff 1 --> 0) | NumErrors: %d \n",j,NumErr_10); printk(KERN_INFO "Loop %d (Buff 0 --> 1) | NumErrors: %d \n",j,NumErr_01); } // ----------------------------------------------------------------------- // Note: devm_kzalloc is managed by the kernel and is freeed automatically return 0; } /************************************************* * Beechwood - Driver remove function * @pdev: Pointer to the platform_device structure * @Return: Always '0' *************************************************/ static int beechwood_dma_removal(struct platform_device *pdev){ struct beechwood_dma_structure *driver_config; driver_config = platform_get_drvdata(pdev); // ---------------------------------- // ------ Print Module Goodbye ------ printk(KERN_INFO "Exit Beechwood DMA testing \n"); // ----------------------------------------------- // ------- Free Previously Allocated Memory ------ dma_free_coherent(driver_config->dev, driver_config->BufferSize_Bytes, driver_config->Buff_Virt_0, driver_config->Buff_Physical0); dma_free_coherent(driver_config->dev, driver_config->BufferSize_Bytes, driver_config->Buff_Virt_0, driver_config->Buff_Physical0); // ------------------------------------ // ------- Unregister Interrupts ------- free_irq(driver_config->S2MM->Channel_IRQ, driver_config->S2MM); free_irq(driver_config->MM2S->Channel_IRQ, driver_config->MM2S); // ------------------------------------------- // ------- Unmap AXI4L IO Memory for DMA ------ iounmap(driver_config->regs); // -------------------------------------- // ------ Unmap the Memory Region ------- release_mem_region(DMA_BASE, DMA_REGION); return 0; } // --------------------------------------------------------------- // --------------------------------------------------------------- // --------------------------------------------------------------- struct beechwood_custom_structure{ float whatever; // Really Arbitrary }; static const struct beechwood_custom_structure Beechwood_Global_Config = { .whatever = 3.14, }; static const struct of_device_id beechwood_compat_table_of_ids[] = { { .compatible = "xlnx,beechwood-dma-driver", .data = &Beechwood_Global_Config }, {} }; // ----------------------------------------------------------------------------------------------------------------------------------------------------- // #1 expose vendor/device id: // #2 At compilation time the build process extracts this infomation from all the drivers and prepares a device table // #3 When you insert the device, the device table is referred by the kernel and if an entry is found matching the device/vendor id of the added device, // then its module is loaded and initialized // ------------------------------------------------------------------------------------------------------------------------------------------------------- MODULE_DEVICE_TABLE(of, beechwood_compat_table_of_ids); /*********************************** * @brief Platform Driver Definition ***********************************/ static struct platform_driver beechwood_driver = { .driver = { .name = "beechwood-dma-driver ", // Driver name .of_match_table = beechwood_compat_table_of_ids, // Compatible table }, .probe = beechwood_dma_probe, // Probe Function .remove = beechwood_dma_removal, // Removal Function }; // ------------------------------------------- // ------- Platfrom Driver Description ------- module_platform_driver(beechwood_driver); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("Custom Direct Register Access Xilinx DMA Kernel Driver"); MODULE_VERSION("1.0"); |
Again, after FPGA bitstream update, device tree changes, module compilation and insertion, you should see a similar output in the kernel log:
Overall, I would say that writing Linux kernel drivers is not that hard, once you know the basics and limitations. The biggest problem is I believe finding a good source of information mostly due to the fact, the the majority of the embedded Linux developers and users just forward you to the code documentation, which is in most cases useless. I really don’t understand this behavior. What is actually sad, that the internet is full of “half-usefull” answers and posts such as i described. That was primarily the reason why I have decided to write this post (Except for the purpose of gaining more experience with driver development). I Hope that my next post regarding the kernel drivers will also include some form of PCIe functionality.