Many of complex IPs and components nowadays use AXI4-Lite interface for configuration. Its a simple and sufficient protocol, but one may wonder how to easily configure such components with these types of interfaces from a Test – Bench.

One of the options is to manually write a well-timed transactions from what is usually a “Stimuli” process in a TB. If there are however plenty of required register writes, this becomes somewhat a messy solution and one may start to think of a better alternative. One of the options is to include a simple AXI4 Lite master in a TB a define only the Addresses and Data to be written there. I personally found this solution quite simple and efficient. The same could be eventually made for read channel, but there are usually no requirements to use read channels at all in a TB. Code below however requires the usage of VHDL2008 standard.

 

 Of course: If you simulate the TB, you should see the following output from a console:

Note: Write to Address: C0FEBABE With Data: 00000001
Time: 135 ns Iteration: 1 Process: /AXI4Lite_TB/TB_AXI4Lite_W_Slave
Note: Write to Address: BEEFBABE With Data: 00000010
Time: 195 ns Iteration: 1 Process: /AXI4Lite_TB/TB_AXI4Lite_W_Slave
Note: Write to Address: DEADC0DE With Data: 00000100
Time: 255 ns Iteration: 1 Process: /AXI4Lite_TB/TB_AXI4Lite_W_Slave
Note: Write to Address: BAADF00D With Data: 00001000
Time: 315 ns Iteration: 1 Process: /AXI4Lite_TB/TB_AXI4Lite_W_Slave
Note: Write to Address: DEADBABE With Data: 00010000
Time: 375 ns Iteration: 1 Process: /AXI4Lite_TB/TB_AXI4Lite_W_Slave
Note: Write to Address: DEADBEAF With Data: 00100000
Time: 435 ns Iteration: 1 Process: /AXI4Lite_TB/TB_AXI4Lite_W_Slave
Note: Write to Address: FEEDC0DE With Data: 01000000
Time: 495 ns Iteration: 1 Process: /AXI4Lite_TB/TB_AXI4Lite_W_Slave

If this solution is not enough,then an alternative would be to use VHDL textio and define addresses and data to be written in a .txt file. This would be a more re-usable solution. Note that the AXI4 Lite Slave shown in the TB supports a minimum of the AXI4 Signals and is always ready to accept data. In a real TB,this process should be switched for a custom DUT. You can read more about AXI4 / AXI4Lite specification at ARM Developer site.