Understanding PCIe to AXI Bridge

Understanding PCIe to AXI Bridge

The most basic setup of simulating/using PCIe on Xilinx FPGA / SoC devices is having a single endpoint (EP) and a single Root Complex (RC). One may accomplish this by instantiating only the base Hard IP Wrappers (Consisting of Physical Layer, Data Link Layer and...
Linux kernel driver development for Zynq/ZynqMP

Linux kernel driver development for Zynq/ZynqMP

I remember that when I first searched for a guide on how to write Linux kernel drivers, the first suggestion mentioned was that I should actually avoid writing kernel drivers. I would personally not suggest the same, though the fact remains that writing kernel drivers...