by Aenerine | Jul 14, 2021 | FPGA
The most basic setup of simulating/using PCIe on Xilinx FPGA / SoC devices is having a single endpoint (EP) and a single Root Complex (RC). One may accomplish this by instantiating only the base Hard IP Wrappers (Consisting of Physical Layer, Data Link Layer and...
by Aenerine | Feb 8, 2021 | FPGA
The times when designers used to calculate and adjust manually delay across PCBs to match a device’s requirements (Such as a memory or ADC/DAC interface) for a few megatransfers / second are definitely over nowadays. Even though they are still used on some...
by Aenerine | Aug 29, 2020 | Quick Posts
There are many possibilities of how you might debug your FPGA design. The most straigtforward way is to use the Chipscope (ILA – Integrated Logic Analyzer), which is accessed by JTAG interface. This is very practical, but it is intended for debug only. What if...
by Aenerine | Aug 23, 2020 | FPGA
I remember that when I first searched for a guide on how to write Linux kernel drivers, the first suggestion mentioned was that I should actually avoid writing kernel drivers. I would personally not suggest the same, though the fact remains that writing kernel drivers...
by Aenerine | Feb 20, 2020 | FPGA
Most of newer ADCs and DACs tend to use the JESD204b/c standards simply due to higher performance requirements – the ever growing need for more usable Bandwidth, faster ADCs and DACs with increased resolution per sample and multi-channel implementations. The...
