by Aenerine | Mar 27, 2021 | Quick Posts
Many of complex IPs and components nowadays use AXI4-Lite interface for configuration. Its a simple and sufficient protocol, but one may wonder how to easily configure such components with these types of interfaces from a Test – Bench. One of the options is to...
by Aenerine | Feb 8, 2021 | FPGA
The times when designers used to calculate and adjust manually delay across PCBs to match a device’s requirements (Such as a memory or ADC/DAC interface) for a few megatransfers / second are definitely over nowadays. Even though they are still used on some...
by Aenerine | Dec 28, 2019 | FPGA
Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks,...
by Aenerine | Dec 23, 2019 | FPGA
by Aenerine | Nov 10, 2019 | FPGA
This topic will introduce some of the basic concept of using fixed point representation in FPGA. Because naturally in FPGAs, there is nothing like a “data format”,but only vector with some bits of data,its always a good idea to negotiate and or describe...
