Simple AXI4 Lite DUT Configuration for TB

Simple AXI4 Lite DUT Configuration for TB

Many of complex IPs and components nowadays use AXI4-Lite interface for configuration. Its a simple and sufficient protocol, but one may wonder how to easily configure such components with these types of interfaces from a Test – Bench. One of the options is to...
Aurora 8/10B Transceiver GTY Serdes

Aurora 8/10B Transceiver GTY Serdes

The times when designers used to calculate and adjust manually delay across PCBs to match a device’s requirements (Such as a memory or ADC/DAC interface) for a few megatransfers / second are definitely over nowadays. Even though they are still used on some...
IP Simulation with custom data

IP Simulation with custom data

Using the Build-in Vivado Simulator or QuestaSim or any other simulator is great for analyzing the RTL and verification of FSMs, signals flow, control and interfacing through I2C, SPI, AXI … Whats a little bit more tricky is the verification of DSP blocks,...
Fixed Point & 2’S Complement

Fixed Point & 2’S Complement

This topic will introduce some of the basic concept of using fixed point representation in FPGA. Because naturally in FPGAs, there is nothing like a “data format”,but only vector with some bits of data,its always a good idea to negotiate and or describe...